1. Field of the Invention
The invention relates generally to the planar semiconductor power devices. More particularly, this invention relates to an improved and novel closed cell configuration with increased channel density, i.e., the channel width per unit of semiconductor area, for sub-micron planar semiconductor power device.
2. Description of the Prior Art
Conventional technologies have reached a limit to reduce the on-resistance of lateral MOS transistors by increasing the channel width in a given MOS transistor area. Reduction of the on-resistance for a cellular array of MOS transistors is desirable because of the lower power loss and ability to conduct high currents. In low voltage application, e.g., MOSFETS application for a voltage lower than 12 volts, lateral MOSFETs offer lower device resistance than vertical double-diffused metal oxide field effect transistors (VDMOS). However, in design large area lateral MOSFETs, the contribution due to parasitic resistance such as Metal bussing increases. It is well known in the art that a VDMOS can achieve low on resistance when measured in term of a unit area of cellular cells. Such low on-resistance is achieved with whole surface area functioning as a drain electrode. Such configuration allows high density of vertically parallel transistors to connect in parallel. These parallel vertical current channels are formed between a source region, covering a large area of a top surface, and the drain electrode connected to a bottom surface. However, there are applications where the VDMOS transistors cannot be conveniently integrated. Under these circumstances, a lateral MOS transistor is generally used despite the fact that a vertical MOS transistor can achieve a lower on-resistance than the lateral MOS transistors.
In order to overcome this drawback of higher on-resistance, a first and most straightforward way to reduce the on-resistance contribution from metal and contact for a lateral MOS resistance is to increase the width of the contacts and metal stripes However, a greater width of the contact metal stripes increases the areas occupied by the transistor array. The reduction of the on-resistance is obtained at the expense of increasing the areas occupied by the transistor array. For this reason, with a strong demand to miniaturize the electronic devices, this method does not provide an effective solution to reduce the on-resistance of the lateral MOSFET devices.
Various layouts of the cell arrays are explored to achieve the purpose of increasing the channel width per unit area (W/area). FIG. 1A shows an alternate configuration with a stripe cell configuration to obtain large channel width by connecting several MOSFETs in parallel. In these stripe cell arrays, alternating drain and source stripes are placed next to each other so that each drain/source stripe shares with adjacent source/drain thereby reducing the overall area of the device. The increased channel width provided by the stripe cell is able to enhance the power management efficiency in circuits such as switching regulator, low dropout regulators and discrete MOSFET drivers.
FIG. 1B is shows a cellular transistor array implemented with a polysilicon gate mesh. The polysilicon gate mesh formed as square cell. As shown in FIG. 1B, the square cell array further increases the channel width per unit area (W/area) by drawing a mesh of polysilicon lines to form alternating source and drain cells that are connected in parallel by metal. More particularly, in U.S. Pat. No. 5,355,008, a square mesh array is implemented in a MOSFET device. By forming the openings in the polysilicon mesh to be in a diamond shape, i.e., having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.
However, as there are strong demands to provide the semiconductor power devices for larger current switching operations with low on-resistance, there still exists a need to further increase the channel density (W/area). Therefore, it is necessary to provide alternate layout for the lateral transistor cell arrays to further increased the channel width per unit area (W/area). It is also desirable that the on-resistance can be further reduced without sacrificing the transistor areas. Furthermore, it is desirable that the lateral transistor arrays can be manufactured with standard CMOS technologies such that the above discussed difficulties and limitations can be resolved.